傘  昊 准教授

学会活動:

研究業績:

Journal Paper

  1. 陳 広謙, 大澤 衛, 北島 敦, 新井 義明,山下 順, 伊藤 壽, 傘 昊, "スタンダードCMOSを用いたオペアンプの入力バイアス電流低減技術," 電気学会論文誌C(電子・情報・システム部門誌), Vol.140, No.1, pp.9--15, 2020年1月.
  2. C. Pan and H. San,"Experimental Implementation of Delta Sigma AD Modulator Using Dynamic Analog Components With Simplified Operation Phase," IEICE Electronics Express, 2019, Volume 16, Issue 12, Pages 20190280.
  3. C. Pan and H. San,"A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer," IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E102-A, No.3, pp.507-517, March, 2019.
  4. 進藤佑司, 瀬戸謙修, 傘昊, "非2進展開に基づくAD変換器のデジタル回路部面積削減手法," 電気学会論文誌C(電子・情報・システム部門誌), Vol.139, No.1, pp.76--82, 2019年1月.
  5. C. Pan and H. San,“Experimental implementation of ΔΣAD modulator with dynamic analog components,''Analog Integrated Circuits and Signal Processing, Springer, Volume 97, Issue 2, pp 215–223, Nov, 2018.
  6. Y. Watanabe, H. Narita, H. Tsuchiya, T. Matsuura, H. San, M. Hotta, “Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC,'' Analog Integrated Circuits and Signal Processing, Springer, Volume 97, Issue 2, pp 207–214, Nov, 2018.
  7. C. Pan and H. San, “A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer,'' IEICE Trans on Electronics, Vol.E101-C, No.7, pp.480-487, July, 2018.
  8. C. Pan and H. San,“A 2nd-order ΔΣAD Modulator using Dynamic Analog Components with Simplied Operation Phase,'' IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E101-A, No.2, pp.425-433, February, 2018.
  9. H. San, R. Sugawara, M. Hotta, T. Matsuura and K. Aihara, “A 12-bit 1.25MS/s Area-efficient Radix-value Self-estimated Non-binary Cyclic ADC with Relaxed Requirements on Analog Components,'' IEICE Trans on Fundamentals of Electronics,Communications and Computer Sciences, Vol.E100-A, No.2, pp.534-540, Feb. 2017.
  10. 潘 春暉, 傘 昊, “逐次比較量子化器とリングアンプを用いるΔΣAD変調器,” 電子情報通信学会論文誌A J99-A,No.8,pp.262--269,Aug.2016.
  11. T. Makino, Y. Iwata, K. Shinohara, Y. Jitsumatsu, M. Hotta, H. San and K. Aihara, “Rigorous estimates of quantization error for A/D converters based on beta-map,” Nonlinear Theory and Its Applications (NOLTA), IEICE Vol.6, No.1, pp.99–111, January 2015.
  12. R. Sugawara, H. San, K. Aihara and M. Hotta, “Experimental Implementation of Non-binary Cyclic ADCs with Radix-value Estimation Algorithm,” IEICE Trans on Electronics, Vol.E97-C, No.4, pp.308--315, April 2014.
  13. R. Suzuki, T. Maruyama, H. San, K. Aihara and M. Hotta,“Robust Cyclic-ADC Architecture Based on β-Expansion,” IEICE Trans on Electronics, Vol.E96-C, No.4, pp.553--559, April 2013.
  14. H. San, T. Kato, T. Maruyama, K. Aihara and M. Hotta, “Non-Binary Pipeline Analog-to-digital Converter Based on β-Expansion,” IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E96-A, No.2, pp.415--421, Feb. 2013.
  15. 小川智彦, 松浦達治, 小林春夫, 高井伸和, 堀田正生, 傘昊, 阿部彰, 八木勝義, 森俊彦, “逐次比較近似ADC コンパレータ・オフセット影響の冗長アルゴリズムによるディジタル補正技術,” 電子情報通信学会論文誌C Vol.J94-C No.3 pp.68--78, 2011 年3 月.
  16. M. Hotta, M. Kawakami, H. Kobayashi, H. San, N. Takai, T. Matsuura, A. Abe, K. Yagi and T.Mori, “SAR ADC Architecture with Digital Error Correction,” IEEJ Transactions on Electrical and Electronic Engineering, Vol.5, no.6, pp.651--659, Nov. 2010.
  17. 林海軍, 田辺朋之, 元澤篤史, ロレパスカル, 飯塚邦彦, 小林春夫, 傘昊, 高井伸和, “連続時間 バンドパスΔΣAD 変調器のQ 値とループ遅延の影響,” 電子情報通信学会論文誌A Vol.J93-A No.2 pp.107--118, 2010 年2 月.
  18. T. Ogawa, H. Kobayashi, Y. Takahashi, N. Takai, M. Hotta, H. San, T. Matsuura, A. Abe, K.Yagi, and T. Mori, “SAR ADC Algorithm with Redundancy and Digital Error Correction,” IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E93-A, no.2, pp.415--423, February 2010.
  19. H. San and H. Kobayashi, “Noise-coupled Image Rejection Architecture of Complex Bandpass ΔΣAD Modulator,” IEICE Trans on Fundamentals of Electronics,Communications and Computer Sciences,vol.E93-A, no.2, pp.390--394, February 2010.
  20. H. San, H. Konagaya, T. Yamada, H. Lin, H. Kobayashi, K. Ando and C. Murayama, “Noise-Coupled ΔΣAD Modulator with Shared OP-Amp,” 電気学会論文誌C(電子・情報・システム部門誌), vol.129-C, No.12, pp.2167--2173, 2009 年12 月.
  21. 林海軍, 田邊朋之, 傘昊, 小林春夫, “インバータタイプGm -- C バンドパスフィルタの解析と設計,” 電気学会論文誌C(電子・情報・システム部門誌), Vol.129-C, No.8, pp.1483-1489, 2009 年8 月.
  22. H. San and H. Kobayashi, “Cross-Noise-Coupled Architecture of Complex Bandpass ΔΣAD Modulator,”IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E92-A, no.4, pp.998--1003, April 2009.
  23. 光野正志, 木村圭吾, 森偉文樹, 山田佳央, 小林春夫, 小堀康功, 清水一也, 傘昊, “デジタル制御電源用 高時間分解能DPWM回路,” 電子情報通信学会論文誌C Vol.J91-C No.8 pp.418--427, 2008 年8 月.
  24. H. San, H. Konagaya, F. Xu, A. Motozawa, H. Kobayashi, K. Ando, H. Yoshida, C. Murayama, and K. Miyazawa, “Novel Architecture of Feedforward Second-Order Multibit ΔΣAD Modulator,” IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E91-A, no.4, pp.965--970, April 2008.
  25. H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, T. Matasuura, K. Yahagi,J. Kudoh, H. Nakane, M. Hotta, T. Tsukada, K. Mashiko, and A.Wada, “A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm,” IEICE Trans on Electronics, vol.E90-C, no.6, pp.1181--1188, June 2007.
  26. 元澤篤史, 萩原広之, 山田佳央, 小林春夫, 小室貴紀, 傘昊, “マルチバンドパスΔΣ 変調器技術とその応用,” 電子情報通信学会論文誌C Vol.J90-C No.2 pp.143-158, 2007 年2 月.
  27. H. San, A. Hayakawa, Y. Jingu, H.Wada, H. Hagiwara, K. Kobayashi, H. Kobayashi, T. Matsuura,K. Yahagi, J. Kudoh, H. Nakane, M. Hotta, T. Tsukada, K. Mashiko, and A. Wada, “ Complex Bandpass ΔΣAD Modulator Architecture Without I, Q-Path Crossing Layout,” IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E89-A, no.4, pp.908--915, April 2006.
  28. J. Otsuki, H. San, H. Kobayashi, T. Komuro, Y. Yamada, A. Liu, “Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths,” IEICE Trans on Electronics, vol.E88-C, no.6, pp.1290--1294, June 2005.
  29. H. San, H. Kobayashi, S. Kawakami, N. Kuroiwa, “A Noise-Shaping Algorithm of Multi-bit DAC Nonlinearities in Complex Bandpass ΔΣAD Modulators,” IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E87-A, no.4, pp.792--800, April 2004.
  30. H. Kobayashi, M. A. Mohamed Zin, H. Sato, K. Kobayashi, H. San, J. Ichimura, Y. Onaya, N.Kurosawa, Y. Kimura, Y. Yuminaka, K. Tanaka, T. Myono and F. Abe, “High-Speed CMOS Track/Hold Circuit Design,” Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, vol.27, no.1-2, pp.165--176, April 2001.
  31. H. San, H. Kobayashi, T. Myono, T. Iijima and N. Kuroiwa, “Highly-Efficient Low- Voltage-Operation Charge Pump Circuits Using Bootstrapped Gate Transfer Switches”, 電気学会論文誌C(電子・情報・システム部門誌), vol.120-C, No.10, pp.1339--1345, 2000 年10 月.

International Conference Paper

  1. Chunhui Pan, Hao San, Tsugumichi Shibata "A 720uW 77.93dB SNDR ΔΣAD Modulator Using Dynamic Analog Components with Simplified Operation Phase," 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp.442-446, Ishigaki, Japan, November, 2018.
  2. Chunhui Pan, Hao San, "A 6th-Order Complex Bandpass ΔΣAD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer," 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp.447-452, Ishigaki, Japan, November,2018.
  3. S. Yamada, T. Teranishi, C. Pan and H. San, "Complex Bandpass ΔΣAD Modulator using Passive-adder Embedded SAR Quantizer," 2018 International Conference on Analog VLSI Circuits (AVIC), Chiang Mai, Thailand, November, 2018
  4. H. Tsuchiya,Y. Watanabe, K. Chin,H. San, T. Matsuura and M. Hotta “The design of a14-bit 400kSPS Non-binary Pipeline Cyclic ADC," IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2017 (IEEE ISPACS 2017), Xiamen, China, Nov. 2017.
  5. K. Chin,Y. Mishima, Y.Watanabe,H. Tsuchiya,H. San, T. Matsuura and M. Hotta “A 12-Bit 3.3MS/s Pipeline Cyclic ADC with Correlated Level Shifting Technique ," IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2017 (IEEE ISPACS2017), Xiamen, China, Nov. 2017.
  6. Y.Watanabe,K. Chin,H. Tsuchiya,H. San, T. Matsuura and M. Hotta, “Experimental Results of Reconfigurable Non-binary Cyclic ADC," IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2017 (IEEE ISPACS 2017), Xiamen, China, Nov. 2017.
  7. C. Pan, H. San and T. Shibata, “A 2nd-order ΔΣAD Modulator Using Ring Amplifier and SAR Quantizer with Simpli ed Operation Mode," 24th International Conference Mixed Design of Integrated Circuits and Systems, pp.45-49, Bydgoszcz, Poland, June 2017.
  8. K. Inoue, T. Matsuura, A. Hyogo, H. San, “Non-binary Cyclic and Binary SAR Hybrid ADC," 24th International Conference Mixed Design of Integrated Circuits and Systems, pp.105-109, Bydgoszcz, Poland, June 2017.
  9. H. Tsuchiya, A. Uchiyama, Y. Mishima, Y. Watanabe, T. Matsuura, H. San and Masao Hotta, “Non-Binary Cyclic ADC with Correlated Level Shifting Technique," 22nd Asia and South Pacific Design Automation Conference ASP-DAC 2017, pp.17--18,Chiba, Japan, Jan. 2017.
  10. Y. Watanabe, H. Narita, J. Uchita, H. Tsuchiya, T. Matsuura, H. San and Masao Hotta,“A 14bit 80kSPS Non-Binary Cyclic ADC without High Accuracy Analog Components," 22nd Asia and South Pacific Design Automation Conference ASP-DAC 2017, pp.15--16,Chiba, Japan, Jan. 2017.
  11. C. Pan, H. San and T. Shibata, “A 2nd-order ΔΣAD Modulator using Dynamic Amplifier and Dynamic SAR Quantizer," The 2016 International Symposium on Intelligent Signal Processing and Communication Systems (IEEE ISPACS 2016), pp.528--532, Phulet, Thailand, Oct. 2016.
  12. K. Chin, A. Kitajima, Y. Arai, J. Yamashita, H. Ito, and H. San,“Leakage Current Compensation Technique of ESD Protection Circuit for CMOS Operational Amplifier," The 2016 International Symposium on Intelligent Signal Processing and Communication Systems (IEEE ISPACS 2016), pp.518--521, Phulet, Thailand, Oct. 2016.
  13. H. Tsuchiya, A. Uchiyama, Y. Mishima, Y. Watanabe, T. Matsuura, H. San and Masao Hotta,“Experimental Implementation of β-Expansion Cyclic ADC with Correlated Level Shifting Technique," 2016 International Conference on Analog VLSI Circuits, pp.5--9, Boston, USA, Aug. 2016.
  14. Y. Watanabe, H. Narita, J. Uchita, H. Tsuchiya, T. Matsuura, H. San and Masao Hotta,“A 14-bit 80ksps Cyclic ADC Based on β-expansion," 2016 International Conference on Analog VLSI Circuits, pp.11--15, Boston, USA, Aug. 2016.
  15. T. Suzuki, A. Hyogo, T. Matsuura and H. San ,“Non-Binary and Binary Weighted Hybrid Pipeline ADC with estimation," 2016 International Conference on Analog VLSI Circuits, pp.17-20, Boston, USA, Aug. 2016.
  16. C. Pan and H. San, “A Low-Distortion Delta-Sigma Modulator with Ring Ampli er and Passive Adder Embedded SAR Quantizer," The 2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2015), pp.299-302, Bali, Indonesia, Nov. 2015.
  17. Y. Mishima, T. Yamada, A. Uchiyama, T. Matsuura, H. San and M. Hotta, “A 10-bit 10Ms/s Pipeline Cyclic ADC Based on β-Expansion," The 2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2015), pp.294-298, Bali, Indonesia, Nov. 2015.
  18. T.Yamada, T.Matsuura, H.San and M.Hotta “A 10-bit Pipelined Cyclic ADC Based on β-Expansion,” 2014 International Conference on Analog VLSI Circuits, Ho Chi Minh City, Vietnam,Oct. 2014.
  19. H.San, R.Sugawara, M.Hotta, T.Matsuura and K.Aihara, “An Area-efficient 12-bit 1.25MS/s Radix-value Self-estimated Non-binary ADC with Relaxed Requirements on Analog Components,” IEEE Custom Integrated Circuits Conference 2014 (CICC 2014), T-03, San Jose, USA, Sept. 2014.
  20. R.Sugawara R.Suzuki H.San T.Matsuura K.Aihara and M.Hotta, “A beta-expansion Based 10-bit CMOS Cycle ADC with Radix-value Self-correction Technique,” 2013 International Conference on Analog VLSI Circuits, pp.52–57, Montreal, Canada, Oct. 2013.
  21. T.Yamada, R.Sugawara, H.San, T.Matsuura, K.Aihara and M.Hotta, “Robustness of Cyclic ADC Based on beta-expansion,” 2013 International Conference on Analog VLSI Circuits, pp.58–63, Montreal, Canada, Oct. 2013.
  22. T. Makino, Y. Iwata, Y. Jitsumatsu, M. Hotta, H. San, and K. Aihara. “Rigorous analysis of quantization error of an A/D converter based on β-map,” 2013 IEEE Int. Symp. on Circuits and Systems (ISCAS 2013), pp.369-372, Beijing, China, May 2013.
  23. R. Suzuki, T. Maruyama, T. Kato, T. Yamada, H. San, K. Aihara and M. Hotta, “A 10-bits Cyclic ADC Based on β-Expansion,” 2012 Int’l Conference on Analog VLSI Circuits, Valencia, Spain, Oct. 2012.
  24. R. Sugawara, R. Suzuki, H. San, K. Aihara and M. Hotta, “Optimized Structure of Encoder for β-expansion-Based Analog-to-Digital Converter,” 2012 Int’l Conference on Analog VLSI Circuits, Valencia, Spain, Oct. 2012.
  25. T. Maruyama, H. San and M. Hotta, “Robust Switched-Capacitor ADC based on β-expansion,” 2011 IEEJ International Analog VLSI Workshop, pp.171–175, Bali, Indonesia, Nov. 2011.
  26. H. San, T. Kato, T. Maruyama and M. Hotta “Non-Binary Pipeline ADC with β-Encoding,” 2011 IEEJ International Analog VLSI Workshop, pp.177–180, Bali, Indonesia, Nov. 2011.
  27. T. Ogawa, H. Kobayashi, N. Takai, M. Hotta, H. San, T. Matsuura, A. Abe, K. Yagi, T. Mori, “Non-binary SAR ADC with Digital Error Correction for Low Power Applications,” 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010), pp.196–199, Kuala Lumpur, Malaysia, Dec. 2010.
  28. M. Kawakami, N. Kawasaki, M. Hotta, H. San, H. Kobayashi, “Design of SAR ADC with Digital Error Correction using Three Comparators,” 2009 IEEJ International Analog VLSI Workshop, pp.37–42, Chiang Mai, Thailand, Nov. 2009.
  29. H. Konagaya, T. Yamada, H. San and H. Kobayashi, “Novel MASH Architecture of ΔΣAD Modulator,”2009 IEEJ International Analog VLSI Workshop, pp. 32–36, Chiang Mai, Thailand, Nov. 2009.
  30. H. Lin, T. Tanabe, A. Motozawa, P. Lo Re, K. Iizuka, H. Kobayashi, H. San, N. Takai, “Q Factor and Loop Delay Effects Consideration for a Continuous-Time ΔΣAD Modulator,” 2009 IEEJ International Analog VLSI Workshop, pp. 16–21, Chiang Mai, Thailand, Nov. 2009.
  31. H. Lin, A. Motozawa, P. Lo Re, K. Iizuka, H. Kobayashi, H. San, “Study of Q Factor and Loop Delay Effects of a Continuous-Time ΔΣAD Modulator,” The IEEE 8th International Conference on ASIC (ASICON 2009), pp.230–233, Changsha, China, Oct. 2009.
  32. H. San and H. Kobayashi, “Complex Bandpass ΔΣAD Modulator with Noise-coupled Image Rejection,” 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009),pp.357-360, Cancun, Mexico, Aug. 2009.
  33. H. Konagaya, H. Lin, H San, H. Kobayashi, K. Ando, H. Yoshida, C. Murayama and Y. Nisida, “ΔΣAD Modulator for Low Power Application,” 2008 IEEE Asia Pacific Conference on Circuits and Systems, (APCCAS 2008), pp.1232–1235, Macao, China, Dec. 2008.
  34. I. Mori, K. Kimura, Y. Yamada, H. Kobayashi, Y. Kobori, S. Wibowo, K. Shimizu, M. Kono and H. San, “High-Resolution DPWM Generator for Digitally Controlled DC-DC Converters,” 2008 IEEE Asia Pacific Conference on Circuits and Systems, (APCCAS 2008), pp.914–917, Macao, China, Dec. 2008.
  35. T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San and N. Takai, “SAR ADC Algorithms with Redundancy,” 2008 IEEE Asia Pacific Conference on Circuits and Systems, (APCCAS 2008), pp.268–271, Macao, China, Dec. 2008.
  36. H. San and H. Kobayashi, “Complex Bandpass ΔΣAD Modulator with Noise-coupled Architecture,” 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2008),pp.486-489, Knoxville, USA, Aug. 2008.
  37. H. Lin, T. Tanabe, A. Motozawa, H. Kobayashi, H. San and N. Takai, “Design and Analysis of Low Power Inverter-Type Gm-C Bandpass Filter,” 2008 IEEJ International Analog VLSI Workshop, pp. 62-67, Istanbul, Turkey, Aug. 2008.
  38. H. Lin, A. Motozawa, K. Shimizu, Y. Takahashi, M. Uemori, H. Kobayashi, T. Tanabe, N. Takai and H. San, “High Frequency CMOS Gm-C Bandpass Filter Design,” 2007 IEEJ International Analog VLSI Workshop, pp.171-176, Limerick, Ireland, Nov. 2007.
  39. H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa and H. Kobayashi, “A CMOS Complex Multibit ΔΣAD Modulator,” 1st International Topical Meeting on Precision Measurement (ITMPM 2007), pp.179-184, Kiryu, Japan, Sept. 2007. (Invited Paper)
  40. H. Konagaya, H. San, F. Xu, A. Motozawa, H. Kobayashi,  K. Ando, H. Yoshida, C. Murayama, K. Miyazawa and Y. Nishida, “Delta-Sigma ADC Architecture for Power Meter Application,” 1st International Topical Meeting on Precision Measurement (ITMPM 2007), pp.195-198, Kiryu, Japan, Sept. 2007.
  41. H. San, H. Konagaya, F. Xu, A. Motozawa, H. Kobayashi, K. Ando, H. Yoshida, C. Murayama, “Second-Order ΔΣAD Modulator with Novel Feedforward Architecture,” 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2007), pp.148-151, Montreal, Canada, Aug.2007.
  42. H. San, Y. Jingu, H.Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, M. Hotta, “A 2.8-V Multibit Complex Bandpass Delta-Sigma AD Modulator in 0.18μm CMOS,” 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), pp.96-97, Yokohama, Japan, Jan. 2007.
  43. H. San, H. Hagiwara, A. Motozawa, H. Kobayashi, “DWA Algorithms for Multibit Complex Bandpass ΔΣAD Modulators of Arbitrary Signal Band,” 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China, Nov. 2006.
  44. H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayasaka, J. Kudoh, K. Yahagi, T. Matsuura, H. Nakane, H. Kobayashi, M. Hotta, T. Tsukada, K.Mashiko, A.Wada, “A Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm,” Proceedings of 2006 IEEE Asian Solid-State Circuits Conference (A-SSCC 2006), pp.55-58, Hangzhou, China, Nov.2006.
  45. H. San, A. Hayalawa, Y. Jingu, H. Wada, H. Hagiwara, K. Kobayashi, H.Kobayashi,T. Matsuura, K. Yahagi, J. Kudoh, H. Nakane, M. Hotta, T. Tsukada, K. Mashiko, A. Wada, “ Complex Bandpass Delta-Sigma AD Modulator Architecture with Dynamic Matching of I,Q Paths,” 2005 IEEJ International Analog VLSI Workshop, Bordeaux, France, Oct. 2005.
  46. H. San, H. Kobayashi, “Design of Discrete-Time Multi-bit Complex Bandpass ΔΣADModulators,” 10th Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Ph.D. forum (Poster Session), Shanghai, China, Jan 2005.
  47. J. Otsuki, H. San, H. Kobayashi, T. Komuro, “ Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths,” 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), pp. I-205 - I-208, Hiroshima, Japan, July 2004.
  48. H. San, H. Kobayashi, S. Kawakami, N. Kuroiwa, H. Wada, “An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass Delta-Sigma AD Modulators”, IEEE 17th International Conference on VLSI Design & 3rd International Conference on Embedded System Design, pp.151-156, Mumbai, India, Jan. 2004.
  49. H. San, N. Kuroiwa, H. Kobayashi, T. Matsukawa, T. Myono, T. Suzuki and T. Iijima, “Design and Measurement of Highly-Efficient Charge Pump Circuits”, 10th Electronic Devices and Systems Conference 2003, pp.192-198, Brno, Czech Republic, Sept. 2003.
  50. H. San, H. Kobayashi, S. Kawakami, N. Kuroiwa and H. Wada, “A Data-Weighted Averaging Algorithm for Multi-but DAC Nonlinearities in Complex Bandpass Delta-Sigma Modulators,”10th Electronic Devices and Systems Conference 2003, pp.177-191, Brno, Czech Republic, Sept.2003.
  51. M. A. Mohamed Zin, H. Kobayashi, K. Kobayashi, J. Ichimura, H. San, Y. Onaya, Y. Kimura,Y. Yuminaka, Y. Sasaki, K. Tanaka and F. Abe, “A High-Speed CMOS Track/Hold Circuit”, 6th IEEE International Conference on Electronics, Circuits and Systems, pp.1709-1712, Paphos, Cyprus, Sept. 1999.

特許出願

  1. 松浦 達治,兵庫 明, 鈴木 拓真, 井上 晃汰,傘 昊, 名称:A/D変換器. 出願日:2016年10月11日, 出願番号: 特願2016-200421;
  2. 傘昊, 丸山翔, 堀田正生: 名称:アナログ‐デジタル変換器及びアナログ信号をデジタル信号に変換する方法. 出願日:2011年9月22日 出願番号: 特許出願2011-207602; 国際出願日:2012年9月6日, PCT出願番号:PCT/JP2012/072786.
  3. 傘昊, 小林春夫: 名称:Complex Bandpass Deltasigmaad Modulator and Digital Radio Receiver (複素バンドパスΔΣAD 変調器及びデジタル無線受信機), 国際出願番号: PCT/JP2010/052873, 国際出願日: 2010年2月24日, 国際公開番号:WO2010/101058, 国際公開日: 2010年9月10日; 米国出願番号:13/254,333 米国内移行日:2011年9月1日; 欧州出願番号:10748653.2, 欧州移行日:2011年10月4日, 欧州公開番号: 2405580, 欧州公開日: 2012 年1月11日.
  4. 傘昊, 小林春夫: 名称:複素バンドパスΔΣAD 変調器及びデジタル無線受信機. 出願日:2009 年3 月4 日 出願番号: 特許出願2009-50714. 特許番号: 特許5187788, 2013年2月1日.
  5. 清水一也, 元澤篤史, 上森将文, 高橋洋介, 小林春夫, 傘昊, 高井伸和, ロレパスカル, 西田修造: 名称:連続時間ΔΣ 変調器. 出願日:2006 年10 月12 日. 出願番号: 特許出願2006-279230. 公開番号: 特許公開2008-099035.
  6. Hao SAN, Haruo KOBAYASHI, Hiroki Wada, Akira HAYAKAWA,Hiroyuki HAGIWARA, Yoshitaka JINGU, Kazuyuki KOBAYASHI, Toshiro TSUKADA Title: Comlex Band-pass Filter for Use in Digital Radio Receiver and Complex Band-pass Delta- Signa AD Modulator. Application No.: 11/408941 (U.S.). Application Date:April 24, 2006.
  7. Hiroyuki HAGIWARA, Haruo KOBAYASHI, Hao SAN, Atsushi Wada Title: DA Converter Circuits Provided with DA Converter of Segment Switched Capacitor Type. Application No.: 11/157,923 (U.S.). Application Date:June 22, 2005.
  8. Hao SAN, Haruo KOBAYASHI, Hiroki Wada, Atsushi Wada Title: Complex Band-pass ΔΣ AD Modulator for Use in AD Converter Circuit. Application No.: 11/157,848 (U.S.). Application Date:June 22, 2005.
  9. 萩原広之, 元澤篤史, 小林春夫, 傘昊:特願2005-356688 号(PCT/JP2006/315200), 名称:高精度マルチバンドパスΔΣ 変調器. 出願日:2005 年11 月9 日.
  10. 傘昊, 小林春夫, 和田宏樹, 早川晃, 萩原広之, 神宮善敬, 小林和幸, 塚田敏郎: 名称:複素バンドパスフィルタ, 複素バンドパスΔΣAD 変調器, AD変換回路及びデジタル無線受信機. 出願番号: 特許出願2005-175242, 2005 年6 月15 日, 公開番号: 特許公開2006-352455, 2006 年12 月28 日, 特許番号: 特許3992287, 2007 年8 月3 日.
  11. 傘昊, 小林春夫, 和田宏樹, 和田淳: 名称:複素バンドパスΔΣAD 変調器, AD変換回路及びデジタル無線受信機. 出願番号: 特許出願2004-185206, 2004 年6 月23 日, 公開番号: 特許公開2006-013705, 2006 年1 月12 日, 特許番号: 特許3970266, 2007 年6 月15 日.
  12. 萩原広之, 小林春夫, 傘昊, 和田淳:特願2004-185198 号. 名称:DA 変換回路およびそれを用いたΔΣAD 変調器. 出願日:2004 年6 月23 日
  13. 小林春夫, 傘昊, 名野隆夫:特願2000-012705 号. 名称:チャージポンプ回路. 出願日:2000 年1 月21 日

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