M. Hotta, M. Kawakami, H. Kobayashi, H. San, N. Takai, T. Matsuura, A. Abe, K. Yagi and T.Mori, “SAR ADC Architecture with Digital Error Correction,” IEEJ Transactions on Electrical and Electronic Engineering, Vol.5, no.6, pp.651--659, Nov. 2010.
T. Ogawa, H. Kobayashi, Y. Takahashi, N. Takai, M. Hotta, H. San, T. Matsuura, A. Abe, K.Yagi, and T. Mori, “SAR ADC Algorithm with Redundancy and Digital Error Correction,” IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E93-A, no.2, pp.415--423, February 2010.
H. San and H. Kobayashi, “Noise-coupled Image Rejection Architecture of Complex Bandpass ΔΣAD Modulator,” IEICE Trans on Fundamentals of Electronics,Communications and Computer Sciences,vol.E93-A, no.2, pp.390--394, February 2010.
H. San, H. Konagaya, T. Yamada, H. Lin, H. Kobayashi, K. Ando and C. Murayama, “Noise-Coupled ΔΣAD Modulator with Shared OP-Amp,” 電気学会論文誌C(電子・情報・システム部門誌), vol.129-C, No.12, pp.2167--2173, 2009 年12 月.
H. San and H. Kobayashi, “Cross-Noise-Coupled Architecture of Complex Bandpass ΔΣAD Modulator,”IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E92-A, no.4, pp.998--1003, April 2009.
H. San, H. Konagaya, F. Xu, A. Motozawa, H. Kobayashi, K. Ando, H. Yoshida, C. Murayama, and K. Miyazawa, “Novel Architecture of Feedforward Second-Order Multibit ΔΣAD Modulator,”
IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E91-A, no.4, pp.965--970, April 2008.
H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, T. Matasuura, K. Yahagi,J. Kudoh, H. Nakane, M. Hotta, T. Tsukada, K. Mashiko, and A.Wada, “A Second-Order Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm,” IEICE Trans on Electronics, vol.E90-C, no.6, pp.1181--1188, June 2007.
H. San, A. Hayakawa, Y. Jingu, H.Wada, H. Hagiwara, K. Kobayashi, H. Kobayashi, T. Matsuura,K. Yahagi, J. Kudoh, H. Nakane, M. Hotta, T. Tsukada, K. Mashiko, and A. Wada, “ Complex Bandpass ΔΣAD Modulator Architecture Without I, Q-Path Crossing Layout,” IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E89-A, no.4, pp.908--915, April 2006.
J. Otsuki, H. San, H. Kobayashi, T. Komuro, Y. Yamada, A. Liu, “Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths,” IEICE Trans on Electronics, vol.E88-C, no.6, pp.1290--1294, June 2005.
H. San, H. Kobayashi, S. Kawakami, N. Kuroiwa, “A Noise-Shaping Algorithm of Multi-bit DAC Nonlinearities in Complex Bandpass ΔΣAD Modulators,” IEICE Trans on Fundamentals of Electronics, Communications and Computer Sciences, vol.E87-A, no.4, pp.792--800, April 2004.
H. Kobayashi, M. A. Mohamed Zin, H. Sato, K. Kobayashi, H. San, J. Ichimura, Y. Onaya, N.Kurosawa, Y. Kimura, Y. Yuminaka, K. Tanaka, T. Myono and F. Abe, “High-Speed CMOS Track/Hold Circuit Design,” Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, vol.27, no.1-2, pp.165--176, April 2001.
H. San, H. Kobayashi, T. Myono, T. Iijima and N. Kuroiwa, “Highly-Efficient Low- Voltage-Operation Charge Pump Circuits Using Bootstrapped Gate Transfer Switches”, 電気学会論文誌C(電子・情報・システム部門誌), vol.120-C, No.10, pp.1339--1345, 2000 年10 月.
Chunhui Pan, Hao San, Tsugumichi Shibata "A 720uW 77.93dB SNDR ΔΣAD Modulator Using Dynamic Analog Components with Simplified Operation Phase," 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp.442-446, Ishigaki, Japan, November, 2018.
Chunhui Pan, Hao San, "A 6th-Order Complex Bandpass ΔΣAD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer," 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp.447-452, Ishigaki, Japan, November,2018.
S. Yamada, T. Teranishi, C. Pan and H. San, "Complex Bandpass ΔΣAD Modulator using Passive-adder Embedded SAR Quantizer," 2018 International Conference on Analog VLSI Circuits (AVIC), Chiang Mai, Thailand, November, 2018
H. Tsuchiya,Y. Watanabe, K. Chin,H. San, T. Matsuura and M. Hotta “The design of a14-bit 400kSPS Non-binary Pipeline Cyclic ADC," IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2017 (IEEE ISPACS 2017), Xiamen, China, Nov. 2017.
K. Chin,Y. Mishima, Y.Watanabe,H. Tsuchiya,H. San, T. Matsuura and M. Hotta “A 12-Bit 3.3MS/s Pipeline Cyclic ADC with Correlated Level Shifting Technique ," IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2017 (IEEE ISPACS2017), Xiamen, China, Nov. 2017.
Y.Watanabe,K. Chin,H. Tsuchiya,H. San, T. Matsuura and M. Hotta, “Experimental Results of Reconfigurable Non-binary Cyclic ADC," IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2017 (IEEE ISPACS 2017), Xiamen, China, Nov. 2017.
C. Pan, H. San and T. Shibata, “A 2nd-order ΔΣAD Modulator Using Ring Amplifier and SAR Quantizer with Simplied Operation Mode," 24th International Conference Mixed Design of Integrated Circuits and Systems, pp.45-49, Bydgoszcz, Poland, June 2017.
K. Inoue, T. Matsuura, A. Hyogo, H. San, “Non-binary Cyclic and Binary SAR Hybrid ADC," 24th International Conference Mixed Design of Integrated Circuits and Systems, pp.105-109, Bydgoszcz, Poland, June 2017.
H. Tsuchiya, A. Uchiyama, Y. Mishima, Y. Watanabe, T. Matsuura, H. San and Masao Hotta, “Non-Binary Cyclic ADC with Correlated Level Shifting Technique," 22nd Asia and South Pacific Design Automation Conference ASP-DAC 2017, pp.17--18,Chiba, Japan, Jan. 2017.
Y. Watanabe, H. Narita, J. Uchita, H. Tsuchiya, T. Matsuura, H. San and Masao Hotta,“A 14bit 80kSPS Non-Binary Cyclic ADC without High Accuracy Analog Components," 22nd Asia and South Pacific Design Automation Conference ASP-DAC 2017, pp.15--16,Chiba, Japan, Jan. 2017.
C. Pan, H. San and T. Shibata, “A 2nd-order ΔΣAD Modulator using Dynamic Amplifier and Dynamic SAR Quantizer," The 2016 International Symposium on Intelligent Signal Processing and Communication Systems (IEEE ISPACS 2016), pp.528--532, Phulet, Thailand, Oct. 2016.
K. Chin, A. Kitajima, Y. Arai, J. Yamashita, H. Ito, and H. San,“Leakage Current Compensation Technique of ESD Protection Circuit for CMOS Operational Amplifier," The 2016 International Symposium on Intelligent Signal Processing and Communication Systems (IEEE ISPACS 2016), pp.518--521, Phulet, Thailand, Oct. 2016.
H. Tsuchiya, A. Uchiyama, Y. Mishima, Y. Watanabe, T. Matsuura, H. San and Masao Hotta,“Experimental Implementation of β-Expansion Cyclic ADC with Correlated Level Shifting Technique," 2016 International Conference on Analog VLSI Circuits, pp.5--9, Boston, USA, Aug. 2016.
Y. Watanabe, H. Narita, J. Uchita, H. Tsuchiya, T. Matsuura, H. San and Masao Hotta,“A 14-bit 80ksps Cyclic ADC Based on β-expansion," 2016 International Conference on Analog VLSI Circuits, pp.11--15, Boston, USA, Aug. 2016.
T. Suzuki, A. Hyogo, T. Matsuura and H. San ,“Non-Binary and Binary Weighted Hybrid Pipeline ADC with estimation," 2016 International Conference on Analog VLSI Circuits, pp.17-20, Boston, USA, Aug. 2016.
C. Pan and H. San, “A Low-Distortion Delta-Sigma Modulator with Ring Ampli
er and Passive Adder Embedded SAR Quantizer," The 2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2015), pp.299-302, Bali, Indonesia, Nov. 2015.
Y. Mishima, T. Yamada, A. Uchiyama, T. Matsuura, H. San and M. Hotta, “A 10-bit 10Ms/s Pipeline Cyclic ADC Based on
β-Expansion," The 2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2015), pp.294-298, Bali, Indonesia, Nov. 2015.
T.Yamada, T.Matsuura, H.San and M.Hotta “A 10-bit Pipelined Cyclic ADC Based on β-Expansion,” 2014 International Conference on Analog VLSI Circuits, Ho Chi Minh City, Vietnam,Oct. 2014.
H.San, R.Sugawara, M.Hotta, T.Matsuura and K.Aihara, “An Area-efficient 12-bit 1.25MS/s Radix-value Self-estimated Non-binary ADC with Relaxed Requirements on Analog Components,” IEEE Custom Integrated Circuits Conference 2014 (CICC 2014), T-03, San Jose, USA, Sept. 2014.
R.Sugawara R.Suzuki H.San T.Matsuura K.Aihara and M.Hotta, “A beta-expansion Based 10-bit CMOS Cycle ADC with Radix-value Self-correction Technique,” 2013 International Conference on Analog VLSI Circuits, pp.52–57, Montreal, Canada, Oct. 2013.
T.Yamada, R.Sugawara, H.San, T.Matsuura, K.Aihara and M.Hotta, “Robustness of Cyclic ADC Based on beta-expansion,” 2013 International Conference on Analog VLSI Circuits, pp.58–63, Montreal, Canada, Oct. 2013.
T. Makino, Y. Iwata, Y. Jitsumatsu, M. Hotta, H. San, and K. Aihara.
“Rigorous analysis of quantization error of an A/D converter based on β-map,” 2013 IEEE Int. Symp. on Circuits and Systems (ISCAS 2013), pp.369-372, Beijing, China, May 2013.
R. Suzuki, T. Maruyama, T. Kato, T. Yamada, H. San, K. Aihara and M. Hotta, “A 10-bits Cyclic ADC Based on β-Expansion,” 2012 Int’l Conference
on Analog VLSI Circuits, Valencia, Spain, Oct. 2012.
R. Sugawara, R. Suzuki, H. San, K. Aihara and M. Hotta, “Optimized Structure of Encoder for β-expansion-Based Analog-to-Digital Converter,” 2012
Int’l Conference on Analog VLSI Circuits, Valencia, Spain, Oct. 2012.
T. Maruyama, H. San and M. Hotta, “Robust Switched-Capacitor ADC based on β-expansion,” 2011 IEEJ International Analog VLSI Workshop, pp.171–175, Bali, Indonesia, Nov. 2011.
H. San, T. Kato, T. Maruyama and M. Hotta “Non-Binary Pipeline ADC with β-Encoding,” 2011 IEEJ International Analog VLSI Workshop, pp.177–180, Bali, Indonesia, Nov. 2011.
T. Ogawa, H. Kobayashi, N. Takai, M. Hotta, H. San, T. Matsuura, A. Abe, K. Yagi, T. Mori,
“Non-binary SAR ADC with Digital Error Correction for Low Power Applications,” 2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010), pp.196–199, Kuala Lumpur, Malaysia, Dec. 2010.
M. Kawakami, N. Kawasaki, M. Hotta, H. San, H. Kobayashi, “Design of SAR ADC with Digital Error Correction using Three Comparators,” 2009 IEEJ International Analog VLSI Workshop, pp.37–42, Chiang Mai, Thailand, Nov. 2009.
H. Konagaya, T. Yamada, H. San and H. Kobayashi, “Novel MASH Architecture of ΔΣAD Modulator,”2009 IEEJ International Analog VLSI Workshop, pp. 32–36, Chiang Mai, Thailand, Nov. 2009.
H. Lin, T. Tanabe, A. Motozawa, P. Lo Re, K. Iizuka, H. Kobayashi, H. San, N. Takai, “Q Factor and Loop Delay Effects Consideration for a Continuous-Time ΔΣAD Modulator,” 2009 IEEJ International Analog VLSI Workshop, pp. 16–21, Chiang Mai, Thailand, Nov. 2009.
H. Lin, A. Motozawa, P. Lo Re, K. Iizuka, H. Kobayashi, H. San, “Study of Q Factor and Loop Delay Effects of a Continuous-Time ΔΣAD Modulator,” The IEEE 8th International Conference on ASIC (ASICON 2009), pp.230–233, Changsha, China, Oct. 2009.
H. San and H. Kobayashi, “Complex Bandpass ΔΣAD Modulator with Noise-coupled Image Rejection,” 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009),pp.357-360, Cancun, Mexico, Aug. 2009.
H. Konagaya, H. Lin, H San, H. Kobayashi, K. Ando, H. Yoshida, C. Murayama and Y. Nisida, “ΔΣAD Modulator for Low Power Application,” 2008 IEEE Asia Pacific Conference on Circuits and Systems, (APCCAS 2008), pp.1232–1235, Macao, China, Dec. 2008.
I. Mori, K. Kimura, Y. Yamada, H. Kobayashi, Y. Kobori, S. Wibowo, K. Shimizu, M. Kono and H. San, “High-Resolution DPWM Generator for Digitally Controlled DC-DC Converters,” 2008 IEEE Asia Pacific Conference on Circuits and Systems, (APCCAS 2008), pp.914–917, Macao, China, Dec. 2008.
T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San and N. Takai, “SAR ADC Algorithms with Redundancy,” 2008 IEEE Asia Pacific Conference on Circuits and Systems, (APCCAS 2008), pp.268–271, Macao, China, Dec. 2008.
H. San and H. Kobayashi, “Complex Bandpass ΔΣAD Modulator with Noise-coupled Architecture,”
51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2008),pp.486-489, Knoxville, USA, Aug. 2008.
H. Lin, T. Tanabe, A. Motozawa, H. Kobayashi, H. San and N. Takai, “Design and Analysis of Low Power Inverter-Type Gm-C Bandpass Filter,” 2008 IEEJ International Analog VLSI Workshop, pp. 62-67, Istanbul, Turkey, Aug. 2008.
H. Lin, A. Motozawa, K. Shimizu, Y. Takahashi, M. Uemori, H. Kobayashi, T. Tanabe, N. Takai and H. San, “High Frequency CMOS Gm-C Bandpass Filter Design,” 2007 IEEJ International Analog VLSI Workshop, pp.171-176, Limerick, Ireland, Nov. 2007.
H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayakawa and H. Kobayashi, “A CMOS Complex Multibit ΔΣAD Modulator,” 1st International Topical Meeting on Precision Measurement (ITMPM 2007), pp.179-184, Kiryu, Japan, Sept. 2007. (Invited Paper)
H. Konagaya, H. San, F. Xu, A. Motozawa, H. Kobayashi, K. Ando, H. Yoshida, C. Murayama, K. Miyazawa and Y. Nishida, “Delta-Sigma ADC Architecture for Power Meter Application,”
1st International Topical Meeting on Precision Measurement (ITMPM 2007), pp.195-198, Kiryu, Japan, Sept. 2007.
H. San, H. Konagaya, F. Xu, A. Motozawa, H. Kobayashi, K. Ando, H. Yoshida, C. Murayama, “Second-Order ΔΣAD Modulator with Novel Feedforward Architecture,” 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2007), pp.148-151, Montreal, Canada, Aug.2007.
H. San, Y. Jingu, H.Wada, H. Hagiwara, A. Hayakawa, H. Kobayashi, M. Hotta, “A 2.8-V Multibit Complex Bandpass Delta-Sigma AD Modulator in 0.18μm CMOS,” 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007), pp.96-97, Yokohama, Japan, Jan. 2007.
H. San, H. Hagiwara, A. Motozawa, H. Kobayashi, “DWA Algorithms for Multibit Complex Bandpass ΔΣAD Modulators of Arbitrary Signal Band,” 2006 IEEJ International Analog VLSI Workshop, Hangzhou, China, Nov. 2006.
H. San, Y. Jingu, H. Wada, H. Hagiwara, A. Hayasaka, J. Kudoh, K. Yahagi, T. Matsuura, H. Nakane, H. Kobayashi, M. Hotta, T. Tsukada, K.Mashiko, A.Wada, “A Multibit Complex Bandpass ΔΣAD Modulator with I, Q Dynamic Matching and DWA Algorithm,” Proceedings of 2006 IEEE Asian Solid-State Circuits Conference (A-SSCC 2006), pp.55-58, Hangzhou, China, Nov.2006.
H. San, A. Hayalawa, Y. Jingu, H. Wada, H. Hagiwara, K. Kobayashi, H.Kobayashi,T. Matsuura, K. Yahagi, J. Kudoh, H. Nakane, M. Hotta, T. Tsukada, K. Mashiko, A. Wada, “ Complex Bandpass Delta-Sigma AD Modulator Architecture with Dynamic Matching of I,Q Paths,” 2005 IEEJ International Analog VLSI Workshop, Bordeaux, France, Oct. 2005.
H. San, H. Kobayashi, “Design of Discrete-Time Multi-bit Complex Bandpass ΔΣADModulators,”
10th Asia and South Pacific Design Automation Conference (ASP-DAC 2005), Ph.D. forum (Poster Session), Shanghai, China, Jan 2005.
J. Otsuki, H. San, H. Kobayashi, T. Komuro, “ Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths,” 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), pp. I-205 - I-208, Hiroshima, Japan, July 2004.
H. San, H. Kobayashi, S. Kawakami, N. Kuroiwa, H. Wada, “An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass Delta-Sigma AD Modulators”, IEEE 17th International Conference on VLSI Design & 3rd International Conference on Embedded System Design, pp.151-156, Mumbai, India, Jan. 2004.
H. San, N. Kuroiwa, H. Kobayashi, T. Matsukawa, T. Myono, T. Suzuki and T. Iijima, “Design and Measurement of Highly-Efficient Charge Pump Circuits”, 10th Electronic Devices and Systems Conference 2003, pp.192-198, Brno, Czech Republic, Sept. 2003.
H. San, H. Kobayashi, S. Kawakami, N. Kuroiwa and H. Wada, “A Data-Weighted Averaging Algorithm for Multi-but DAC Nonlinearities in Complex Bandpass Delta-Sigma Modulators,”10th Electronic Devices and Systems Conference 2003, pp.177-191, Brno, Czech Republic, Sept.2003.
M. A. Mohamed Zin, H. Kobayashi, K. Kobayashi, J. Ichimura, H. San, Y. Onaya, Y. Kimura,Y. Yuminaka, Y. Sasaki, K. Tanaka and F. Abe, “A High-Speed CMOS Track/Hold Circuit”, 6th IEEE International Conference on Electronics, Circuits and Systems, pp.1709-1712, Paphos, Cyprus, Sept. 1999.